1. Field of the Invention
Generally, the present disclosure relates to integrated circuits and, more particularly, to transistors comprising a high-k metal gate electrode structure formed in an early manufacturing stage.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistors, which represent the dominant circuit elements in complex integrated circuits. For example, several hundred million transistors may be provided in presently available complex integrated circuits, wherein performance of the transistors in the speed critical signal paths substantially determines overall performance of the integrated circuit. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, the complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface positioned between highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
When reducing the channel length of field effect transistors, generally an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high speed transistor elements, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may become increasingly incompatible with thermal power requirements of sophisticated integrated circuits, in some approaches, the inferior controllability of the channel region of the short channel transistors caused by the continuous reduction of the critical dimensions of gate electrode structures has been addressed by an appropriate adaptation of the material composition of the gate dielectric material.
To this end, it has been proposed that, for a physically appropriate thickness of a gate dielectric material, i.e., for a thickness resulting in an acceptable level of gate leakage currents, a desired high capacitive coupling may be achieved by using appropriate material systems, which have a significantly higher dielectric constant compared to the conventionally used silicon dioxide-based materials. For example, dielectric materials including hafnium, zirconium, aluminum and the like may have a significantly higher dielectric constant and are therefore referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher when measured in accordance with typical measurement techniques. As is well known, the electronic characteristics of the transistors also strongly depends on the work function of the gate electrode material, which in turn influences the band structure of the semiconductor material in the channel regions separated from the gate electrode material by the gate dielectric layer. In well-established polysilicon/silicon dioxide-based gate electrode structures, the corresponding threshold voltage that is strongly influenced by the gate dielectric material and the adjacent electrode material is adjusted by appropriately doping the polysilicon material in order to appropriately adjust the work function of the polysilicon material at the interface between the gate dielectric material and the electrode material. Similarly, in gate electrode structures including a high-k gate dielectric material, the work function has to be appropriately adjusted for N-channel transistors and P-channel transistors, respectively, which may require appropriately selected work function adjusting metal species, such as lanthanum for N-channel transistors and aluminum for P-channel transistors and the like. For this reason, corresponding metal-containing conductive materials may be positioned close to the high-k gate dielectric material in order to form an appropriately designed interface that results in the target work function of the gate electrode structure. In some conventional approaches, the work function adjustment is performed at a very late manufacturing stage, i.e., after any high temperature processes, after which a placeholder material of the gate electrode structures, such as polysilicon, is replaced by an appropriate work function adjusting species in combination with an electrode metal, such as aluminum and the like. In this case, however, very complex patterning and deposition process sequences are required in the context of gate electrode structures having critical dimensions of 50 nm and significantly less, which may result in severe variations of the resulting transistor characteristics.
Therefore, other process strategies have been proposed in which the work function adjusting materials may be applied in an early manufacturing stage, i.e., upon forming the gate electrode structures, wherein the metal species may be thermally stabilized and encapsulated in order to obtain the desired work function and thus threshold voltage of the transistors without being unduly influenced by the further processing. It turns out that, for many appropriate metal species and metal-containing electrode materials, an appropriate adaptation of the band gap of the channel semiconductor material may be required, for instance, in some P-channel transistors, in order to appropriately set the work function thereof. For this reason, frequently, a so-called threshold adjusting semiconductor material, for instance in the form of a silicon/germanium mixture, is formed on the active regions of these P-channel transistors prior to forming the gate electrode structures, thereby obtaining the desired offset in the band gap of the channel semiconductor material.
With reference to FIGS. 1a-1c, a conventional process technique will now be described in more detail, in which a threshold voltage adjusting semiconductor material may be selectively formed in some transistors, while other transistors are appropriately masked.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a very advanced manufacturing stage. As shown, the semiconductor device 100 comprises a substrate 101, such as a silicon substrate and the like, on which is formed a semiconductor layer 102, such as a silicon layer, which in turn is laterally divided into a plurality of active regions 102A, 102B. To this end, appropriate isolation structures, such as a shallow trench isolation region 102C, are provided so as to separate and laterally delineate the active regions 102A, 102B. In the manufacturing stage shown, a first transistor 150A is formed in and above the active region 102A and comprises a sophisticated high-k metal gate electrode structure 160A. As discussed above, the gate electrode structure 160A is formed on a silicon/germanium material 103A that has an appropriate thickness and material composition, i.e., germanium concentration, so as to obtain a desired band gap offset with respect to the silicon base material of the active regions 102A, 102B. Consequently, the silicon/germanium material 103A represents a part of the active region 102A and results in an appropriate work function and thus threshold voltage for the transistor 150A, which is a P-channel transistor that requires a dedicated threshold voltage. To this end, the gate electrode structure 160A typically comprises a gate dielectric layer 161A, which is provided in the form of a high-k dielectric material having a dielectric constant of 10.0 or higher. It should be appreciated that the gate dielectric material 161A may comprise a conventional dielectric material, such as a silicon oxynitride material and the like, in combination with a specific high-k material, such as hafnium oxide and the like. Furthermore, the gate electrode structure 160A comprises a metal-containing electrode material 162A, for instance in the form of titanium nitride, which may include additional work function metals, such as aluminum and the like. In other cases, an appropriate work function metal may be incorporated in a portion of the gate dielectric material 161A, depending on the overall process strategy used for forming the gate electrode structure 160A.
Consequently, the threshold voltage adjusting material 103A in combination with the materials 161A, 162A substantially determined the threshold characteristics of the P-channel transistor 150A for otherwise given transistor characteristics.
Additionally, the gate electrode structure 160A comprises a further electrode material 163, such as a polysilicon material, and a protective liner or spacer 164, which is provided so as to confine any sidewall areas of sensitive materials, such as the gate dielectric material 161A and the electrode material 162A. Furthermore, a sidewall spacer structure 165 is typically provided so as to have an appropriate configuration that enables the formation of drain and source regions 152 having an appropriate lateral and vertical dopant profile. Consequently, on the basis of the appropriately designed drain and source regions 152 and the material 103A, in combination with the gate electrode structure 160A, a channel region 151 is defined in the active region 102A so as to provide the required electronic characteristics in order to obtain a desired threshold voltage for the transistor 150A.
Similarly, a second transistor 150B, such as an N-channel transistor, is formed in and above the active region 102B and comprises a gate electrode structure 160B that typically has a similar configuration as the gate electrode structure 160A. In order to comply with the threshold voltage requirements of the N-channel transistor 150B, the corresponding gate dielectric material 161B, which is also a high-k dielectric material, and/or a metal-containing electrode material 162B comprise an appropriate work function metal, such as lanthanum and the like, so as to obtain a desired work function and thus threshold voltage in combination with the specific dopant profiles of the drain and source regions 152.
The semiconductor device 100 as shown in FIG. 1A may be formed on the basis of the following processes. In an early manufacturing stage, the isolation region 102C is formed by applying well-established lithography, etch, deposition, anneal and planarization techniques so as to form trenches in the semiconductor layer 102 and filling the trenches with an appropriate dielectric material. By providing the isolation regions 102C, the lateral size and shape of the active regions 102A, 102B are defined. Next, the active region 102B is masked, for instance, by forming an appropriate dielectric material, such as an oxide material and the like, selectively above the active region 102B, which may be accomplished on the basis of well-established oxidation and/or deposition techniques in combination with appropriate lithography strategies, so as to remove any dielectric material from the active region 102A. Thereafter, the resulting surface of the active region 102A is conditioned, i.e., prepared, for the subsequent selective deposition of the silicon/germanium material 103A. To this end, well-established wet chemical processes are applied so as to remove native oxide and any other contaminants prior to performing a selective epitaxial growth process. If required, the active region 102A may be recessed prior to actually depositing the material 103A. In this manner, a superior overall surface topography may be accomplished. Thereafter, the dielectric mask material formed above the active region 102B is removed and the further processing is continued by depositing appropriate materials for the dielectric gate layers 161A, 161B and the metal-containing electrode materials 162A, 162B. It should be appreciated that, depending on the specific process strategy, providing an appropriate work function metal may involve the deposition of respective metal layers, which are then appropriately patterned and subjected to a heat treatment in order to diffuse the corresponding work function metal into the lower lying gate dielectric material 161A, 161B, respectively. In other cases, specific work function metal layers are deposited in the form of the layers 162A, 162B followed by the deposition of the material 163 and any further sacrificial materials, such as hard mask materials and the like as required for patterning the resulting layer stack. Next, a highly complex patterning sequence is applied so as to pattern the layer stack on the basis of the corresponding design rules, which may require a gate length of 50 nm and significantly less in sophisticated applications. In this patterning sequence, complex lithography processes have to be applied in combination with complex etch techniques, wherein the presence of any surface irregularities, material non-uniformities and the like may significantly affect the final patterning results.
By providing the materials 161A, 162A, 161B, 162B in combination with the material 103A, the transistor characteristics are basically determined in an early manufacturing stage, in combination with the complex dopant profile for the drain and source regions 152, still to be formed, so that any undue variation of the electronic characteristics of the gate electrode structures 160A, 160B during the further processing are to be avoided. In particular, the sensitive materials 161A, 162A and 161B, 162B have to be reliably confined, which is accomplished by providing the liner 164, for instance in the form of a highly conformal and stable silicon nitride material.
Thereafter, the further processing is continued by forming the drain and source regions 152 in combination with the spacer structure 165, which is accomplished by applying well-established process techniques. Finally, sophisticated anneal processes, such as laser-based anneal techniques and the like, are frequently applied, in particular when highly scaled transistors are considered.
Upon applying the above-described process sequence, however, it turns out that a significant variation of transistor characteristics, in particular a variation of the threshold voltage, in particular of N-channel transistors, may be observed, as will be explained in more detail with reference to FIGS. 1b and 1c. 
FIG. 1b schematically illustrates a top view of the device 100, wherein the transistor 150B is illustrated only, since the threshold valuations are particularly pronounced in N-channel transistors, as discussed above. In FIG. 1B, the transistor 150B has a specific width, as indicated by 102W, which substantially determines the current drive capability of the transistor 150B. Without intending to restrict the present application to any specific theory, it is assumed that, in particular during any new processes performed at a final stage so as to re-crystallize implantation-induced damage and activate drain and source dopant species, a significant modification may occur locally in the sensitive materials of the gate electrode structure 160B. For example, during a laser anneal process, the temperature of a corresponding portion of the device 100 may be locally increased within a thickness of several micrometers, thereby facilitating the migration of dopant species to a next lattice site. During the time interval of elevated temperature acting on the transistor 150B, and in particular on the gate electrode structure 160B, it is assumed that a modification may take place in the sensitive materials 161B, 162B (FIG. 1a). For example, it is assumed that high-k dielectric materials may have an increased affinity to oxygen, while also a certain degree of oxygen migration may occur during high temperature processes, which may result in a certain amount of oxygen vacancies, according to some non-confirmed theories. During the anneal process, therefore, oxygen may be incorporated into the gate electrode structure 160B, preferably from the edges 102E of the active region 102B, for instance due to the presence of the isolation region 102C, at areas in which the gate electrode structure 160B is in contact with the isolation region 102C. Consequently, it is believed that an increased oxygen ingress into the gate electrode structure 160B may be induced due to laser-based anneal processes. Although the reason is still unknown, a corresponding modification may occur in N-channel transistors to a significantly higher degree compared to P-channel transistors. Thus, the characteristics of the gate electrode structure 160B may be locally modified in the transistor 150B and may thus result, for instance, in a significant shift of the threshold voltage locally at corresponding edges of the active region 102B, which may thus also result in a shift of threshold voltage for the entire transistor 150B. Since the corresponding modification of the high-k dielectric material and/or of the corresponding conductive cap material may be locally restricted to the corresponding edge regions, the overall influence on the transistor 150B may be higher for a reduced transistor width.
FIG. 1c schematically illustrates a top view of the device 100 when the transistor 150B represents a transistor of reduced width. Since here the sphere of influence on the gate electrode structure 160B may be comparable to the situation as shown in FIG. 1B, in total the influence on the overall threshold voltage of the transistor 150B having the reduced transistor width is significantly more pronounced compared to the device as shown in FIG. 1b, so that generally the transistors 150B of different width may have a different threshold voltage.
As a consequence, since typically a plurality of different transistor widths may have to be implemented in complex semiconductor devices, a pronounced variation of the threshold voltages with transistor width may be observed, in particular for N-channel transistors.
It has been realized that the incorporation of carbon at and near the surface of the active regions, in particular in N-channel transistors, significantly improves the situation and resides in superior stability of the threshold voltage of N-channel transistors of different transistor width.
FIG. 1d schematically illustrates a cross-sectional view of the semiconductor device 100, in which the transistors 150A, 150B have basically the same configuration as discussed earlier, wherein, however, a carbon species 104 is incorporated into the active regions 102A, 102B. Typically, the carbon species 104 is incorporated on the basis of an ion implantation process, which is performed in an early manufacturing stage, as will be described with reference to FIGS. 1e and 1f. 
FIG. 1e schematically illustrates the semiconductor device 100 during an ion implantation process 110 in order to introduce the carbon species 104 into the active regions 102A, 102B. In the process strategy shown in FIG. 1e, a deposition mask 105, such as a silicon dioxide material, for instance formed by oxidation, as indicated by the dashed line, a silicon nitride material, and the like may be provided so as to reliably cover the active region 102B, while exposing the active region 102A in order to subsequently form the threshold voltage adjusting semiconductor material. During the implantation process 110, which is typically performed on the basis of an implantation energy of several keV with an implantation dose of approximately 1×1014 to 4×1014 cm−2, the carbon species 104 is incorporated through the mask 105 so as to extend to an appropriate depth. It has been recognized that the presence of the carbon species 104 in the active region 102A may also be highly advantageous with respect to reducing the overall crystalline defects upon forming the threshold voltage adjusting semiconductor material.
FIG. 1f schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, the material 103A is formed selectively in the active region 102A, while the active region 102B is still covered by the deposition mask 105. Thereafter, the further processing may be continued on the basis of process techniques as is also described above. For example, depending on the overall process strategy, prior to or after providing the threshold voltage adjusting semiconductor material 103A, appropriate dopant species are introduced into the active regions 102A, 102B by applying appropriate masking regimes and implantation techniques.
Although the above-described process sequence is highly efficient in incorporating a carbon species, which in turn may significantly improve transistor performance and reduce threshold voltage variations, in particular in N-channel transistors, it has been observed that pronounced yield losses may occur, which are mainly associated with gate failures.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.